LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 286
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
18.6.3 A/D Status Register (AD0STAT - 0x4001 C030)
18.6.4 A/D Interrupt Enable Register (AD0INTEN - 0x4001 C00C)
18.6.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4001 C010 to
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 281: A/D Status Register (AD0STAT - address 0x4001 C030) bit description
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 282: A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description
0x4001 C02C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Bit
7:0
15:8
16
31:17 -
Bit
7:0
8
31:9 -
Symbol
ADINTEN 7:0 These bits allow control over which A/D channels generate
ADGINTEN
Symbol
Done7:0
Overrun7:0 These bits mirror the OVERRRUN status flags that appear in the
ADINT
All information provided in this document is subject to legal disclaimers.
These bits mirror the DONE status flags that appear in the result
This bit is the A/D interrupt flag. It is one when any of the individual
Description
register for each A/D channel.
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.
Reserved.
Description
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Reserved.
Rev. 2 — 7 July 2010
Chapter 18: LPC13xx Analog-to-Digital Converter (ADC)
UM10375
© NXP B.V. 2010. All rights reserved.
288 of 333
Reset
Value
0
0
0
0
Reset
Value
0x00
1
0
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