LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 148
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
9.13 Functional description
UM10375
User manual
9.12.2 USB device controller initialization
9.13.1 Data flow from the Host to the Device
10. Set USB clock by setting USBCLKSEL (see
11. Update clock source by setting 1 in USBPLLUEN (see
12. Set USB clock divider register (see
The USB ATX receives the bi-directional USB_DP and USB_DM lines of the USB bus. It
will put this data in the unidirectional interface between ATX and USB block.
The SIE protocol engine receives this serial data and converts it into a parallel data
stream. The parallel data is sent to the RAM interface which in turn will transfer the data to
the endpoint buffer. The endpoint buffer is implemented as an SRAM based FIFO. Data is
written to the buffers with the header showing how many bytes are valid in the buffer.
For non-isochronous endpoints when a full data packet is received without any errors, the
endpoint generates a request for data transfer from its FIFO by generating an interrupt to
the system.
7. Enable the main system PLL by clearing bit 7 in PDAWAKECFG (see
8. If the USB PLL is used as the USB clock, do the following extra step:
9. Enable USB clock by clearing bit 8 in PDCTRL.
1. Set bits 14 and 16 in the AHBCLKCTRL register (see
2. In the IOConfig block, set Port0[3] (see
3. Clear any device interrupts using USBDevIntClr
4. Install the USB interrupt handler in the NVIC.
5. Set the default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
6. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
wait until the PLL clock is locked.
Configure USB PLL identically to the System PLL and select system clock source by
setting 0x01 (use system oscillator) in USBPLLCLKSEL (see
a. 0x0 if USB PLL is used.
b. 0x1 if main clock is used.
USB clock source is updated.
by 1, as the input is 48 MHz already.
IOConfig blocks. The IOConfig is needed to configure IO pin multiplexing.
USB VBUS and USB CONNECT respectively.
endpoints by setting the corresponding bits in USBDevIntEn
command.
command.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Table
Table
Chapter 9: LPC13xx USB device controller
30) to 1, meaning the USB clock is divided
Table
101) and Port0[6] (see
(Table
28) to:
Table
Table
158), then enable the desired
23) to enable USB and
19) register and wait until
(Table
Table
UM10375
© NXP B.V. 2010. All rights reserved.
28) register.
157).
Table
Table
109) to
51), then
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