LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 233

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

13.1 How to read this chapter
13.2 Basic configuration
13.3 Features
13.4 General description
UM10375
User manual
The SSP block is identical for all LPC13xx parts.
The SSP is configured using the following registers:
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC13xx has one Synchronous Serial Port controller.
1. Pins: The SSP pins must be configured in the IOCONFIG register block
2. Power: In the SYSAHBCLKCTRL register, set bit 11
3. Peripheral clock: Enable the SSP peripheral clock by writing to the SSP0CLKDIV
4. Reset: Before accessing the SSP block, ensure that the SSP_RST_N bit (bit 0) in the
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UM10375
Chapter 13: LPC13xx SSP
Rev. 2 — 7 July 2010
(Section
register
PRESETCTRL register
SSP block.
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Supports master or slave operation.
Eight frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
(Table
6.4.1).
All information provided in this document is subject to legal disclaimers.
24).
Rev. 2 — 7 July 2010
(Table
7) is set to 1. This de-asserts the reset signal to the
(Table
23).
© NXP B.V. 2010. All rights reserved.
User manual
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