LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 2

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Revision history
Contact information
For more information, please visit:
For sales office addresses, please send an email to:
UM10375
User manual
Rev
2
1
Date
20100707
20091106
Description
LPC1311/13/42/43 user manual
Modifications:
LPC1311/13/42/43 user manual
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt handling registers added to NVIC chapter.
Description of bootloader revisions added in
Description of power management updated in
Description of register PDSLEEPCFG updated in
register (PDSLEEPCFG, address 0x4004 8230) bit
Editorial updates throughout the manual.
Handling of clock switching updated in
Description of Systick timer and register names updated in
Reset value of the PRESETCTRL register corrected
Bit 8 added to PCON register
Pin functions TRST, TDO, TMS, TDI changed to R (Reserved) throughout the
document.
Description of GPIOnDATA register updated
SSP time-out value added in
Description of flash content protection added
U0FIFOLVL register removed in
V
PLL configuration examples added
Document template updated.
Basic configuration sections added.
Watchdog oscillator frequency spread changed to ± 40% over processing and
temperature
Inputs to the system oscillator changed (watchdog oscillator removed) in the system
control block,.
Remove PLL modes “direct CCO mode”, “bypass mode”, and “direct bypass mode” in
the system control block.
Editorial updates to the GPIO chapter.
Editorial updates to the I
Editorial updates to the System control chapter.
Reset values of SYSAHBCTRL register updated.
DD(3V3)
http://www.nxp.com
All information provided in this document is subject to legal disclaimers.
and V
(Section
DD(IO)
Rev. 2 — 7 July 2010
combined to V
3.5.8).
[e-mail]
2
C chapter.
Chapter
(Table
Chapter
DD
(Table
58).
13.
throughout the user manual.
Chapter
11.
55).
Section
(Section
(Section
Section 3.8 “Power
3.
Table 50 “Deep-sleep configuration
description”.
(Table
19.2.
8.4.1).
19.6).
Chapter
7).
LPC13xx User manual
management”.
UM10375
© NXP B.V. 2010. All rights reserved.
16.
2 of 333