LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 169

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
11.6.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when
Table 189. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1)
Table 190. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when
DLAB = 0)
The U0IER is used to enable the four UART interrupt sources.
Table 191. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Bit
0
1
2
3
6:4
7
8
9
31:10 -
Symbol
DLLSB
Symbol
DLMSB
Symbol
RBR
Interrupt
Enable
THRE
Interrupt
Enable
RX Line
Interrupt
Enable
-
-
-
ABEOIntEn
ABTOIntEn
bit description
DLAB = 1) bit description
description
All information provided in this document is subject to legal disclaimers.
Description
The UART Divisor Latch LSB Register, along with the U0DLM
register, determines the baud rate of the UART.
Reserved
Description
The UART Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UART.
Reserved
Value
0
1
0
1
0
1
0
1
0
1
-
-
Rev. 2 — 7 July 2010
Description
Enables the Receive Data Available interrupt for UART. It
also controls the Character Receive Time-out interrupt.
Disable the RDA interrupt.
Enable the RDA interrupt.
Enables the THRE interrupt for UART. The status of this
interrupt can be read from U0LSR[5].
Disable the THRE interrupt.
Enable the THRE interrupt.
Enables the UART RX line status interrupts. The status of
this interrupt can be read from U0LSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Reserved
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x01
-
Reset value
0x00
-
171 of 333
Reset
value
0
0
0
-
NA
0
0
0
NA