LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 297

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
19.12.1 ISP entry protection
Table 289. Code Read Protection hardware/software interaction
Table 290. ISP commands allowed for different CRP levels
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupported or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
In addition to the three CRP modes, the user can prevent the sampling of pin PIO0_1 for
entering ISP mode and thereby release pin PIO0_1 for other uses. This is called the
NO_ISP mode. The NO_ISP mode can be entered by programming the pattern
0x4E69 7370 at location 0x0000 02FC.
The NO_ISP mode is identical to the CRP3 mode except for SWD access, which is
allowed in NO_ISP mode but disabled in CRP3 mode. The NO_ISP mode does not offer
any code protection.
CRP option
CRP2
CRP2
CRP3
CRP1
CRP2
CRP3
ISP command
Unlock
Set Baud Rate
Echo
Write to RAM
Read Memory
Prepare sector(s) for
write operation
Copy RAM to flash
Go
Erase sector(s)
Blank check sector(s)
Read Part ID
Read Boot code version yes
Compare
ReadUID
User Code
Valid
Yes
Yes
Yes
No
No
No
All information provided in this document is subject to legal disclaimers.
CRP1
yes
yes
yes
yes; above 0x1000 0300
only
no
yes
yes; not to sector 0
no
yes; sector 0 can only be
erased when all sectors are
erased.
no
yes
no
yes
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
PIO0_1 pin at
reset
High
Low
x
x
x
x
SWD enabled LPC13xx
No
No
No
No
No
No
CRP2
yes
yes
yes
no
no
yes
no
no
yes; all sectors
only
no
yes
yes
no
yes
enters ISP
mode
No
Yes
No
Yes
Yes
Yes
…continued
CRP3 (no entry in ISP
mode allowed)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
UM10375
© NXP B.V. 2010. All rights reserved.
partial flash
Update in ISP
mode
NA
No
NA
Yes
No
No
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