LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 178

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
11.6.12 UART Auto-baud Control Register (U0ACR - 0x4000 8020)
11.6.11 UART Scratch Pad Register (U0SCR - 0x4000 801C)
Table 199. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description
The U0SCR has no effect on the UART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the U0SCR has occurred.
Table 200. UART Scratch Pad Register (U0SCR - address 0x4000 8014) bit description
The UART Auto-baud Control Register (U0ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Bit Symbol Value Description
0
1
2
3
4
5
6
7
31:
8
Bit Symbol Description
7:0 Pad
31:
8
Delta
CTS
Delta
DSR
Trailing
Edge RI
Delta
DCD
CTS
DSR
RI
DCD
-
-
-
A readable, writable byte.
Reserved
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
0
1
Set upon state change of input CTS. Cleared on a U0MSR read.
No change detected on modem input CTS.
State change detected on modem input CTS.
Set upon state change of input DSR. Cleared on a U0MSR read.
No change detected on modem input DSR.
State change detected on modem input DSR.
Set upon low to high transition of input RI. Cleared on a U0MSR
read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on a U0MSR read.
No change detected on modem input DCD.
State change detected on modem input DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U0MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U0MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected
to U0MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is
connected to U0MCR[3] in modem loopback mode.
Reserved
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
Reset Value
0x00
-
180 of 333
Reset
Value
0
0
0
0
0
0
0
0
-