LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 21

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.12 System PLL clock source update enable register
3.5.13 USB PLL clock source select register
Table 16.
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 17.
This register selects the clock source for the dedicated USB PLL. The USBPLLCLKUEN
register (see
effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated in the USBPLLCLKUEN register. For USB operation, the clock source
must be switched from IRC to system oscillator with both the IRC and the system
oscillator running. After the switch, the IRC can be turned off.
Table 18.
Bit
1:0
31:2
Bit
0
31:1
Bit
1:0
31:2
Symbol
SEL
-
Symbol
ENA
-
Symbol
SEL
-
bit description
0x4004 8044) bit description
USB PLL clock source select register (USBPLLCLKSEL, address 0x4004 8048) bit
description
System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
System PLL clock source update enable register (SYSPLLCLKUEN, address
Section
All information provided in this document is subject to legal disclaimers.
Value
00
01
10
11
-
Value
00
01
10
11
-
Value
0
1
-
3.5.14) must be toggled from LOW to HIGH for the update to take
Rev. 2 — 7 July 2010
Description
System PLL clock source
IRC oscillator
System oscillator
Reserved
Reserved
Reserved
Description
USB PLL clock source
IRC. The USB PLL clock source must be switched to system
oscillator for correct USB operation.
System oscillator
Reserved
Reserved
Reserved
Description
Enable system PLL clock source update
No change
Update clock source
Reserved
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x00
22 of 333
Reset
value
0x00
0x00
Reset
value
0x00
0x00