LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 280

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
17.7.2 Watchdog Timer Constant register (WDTC - 0x4000 4004)
17.7.3 Watchdog Feed register (WDFEED - 0x4000 4008)
17.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C)
Table 273. Watchdog operating modes selection
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
Table 274. Watchdog Constant register (WDTC - address 0x4000 4004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
Table 275. Watchdog Feed register (WDFEED - address 0x4000 4008) bit description
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
WDEN
0
1
1
Bit
31:0
Bit
7:0
31:8
Symbol
Count
Symbol
Feed
-
WDRESET
X (0 or 1)
0
1
All information provided in this document is subject to legal disclaimers.
Description
Watchdog time-out interval.
Description
Feed value should be 0xAA followed by 0x55.
reserved
Rev. 2 — 7 July 2010
Mode of Operation
Debug/Operate without the Watchdog running.
Watchdog interrupt mode: debug with the Watchdog interrupt but no
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the Watchdog interrupt request will be generated.
Watchdog reset mode: operate with the Watchdog interrupt and
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. Although the Watchdog interrupt is also enabled in
this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
Chapter 17: LPC13xx WatchDog Timer (WDT)
WDCLK
× 256 × 4.
UM10375
© NXP B.V. 2010. All rights reserved.
0x0000 00FF
-
Reset Value
Reset Value
NA
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