LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 26

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.21 Trace clock divider register
3.5.22 SYSTICK clock divider register
3.5.23 USB clock source select register
This register configures the ARM trace clock. The trace clock can be shut down by setting
the DIV bits to 0x0.
Table 26.
This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be
shut down by setting the DIV bits to 0x0.
Table 27.
This register selects the clock source for the USB usb_clk. The clock source can be either
the USB PLL output or the main clock, and the clock can be further divided by the
USBCLKDIV register (see
The USBCLKUEN register (see
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated. The default clock source for the USB controller is the USB PLL output.
For switching the clock source to the main clock, ensure that the system PLL and the USB
PLL are running to make both clock sources available for switching. The main clock must
be set to 48 MHz and configured with the main PLL and the system oscillator. After the
switch, the USB PLL can be turned off.
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
DIV
-
Symbol
DIV
-
TRACECLKDIV clock divider register (TRACECLKDIV, address 0x4004 80AC) bit
description
SYSTICK clock divider register (SYSTICKCLKDIV, address 0x4004 80B0) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
to
255
-
Value
0
1
to
255
-
Rev. 2 — 7 July 2010
Description
ARM trace clock divider values
Disable trace clock.
Divide by 1.
...
Divide by 255.
Reserved
Description
SYSTICK clock divider values
Disable SYSTICK timer clock.
Divide by 1.
...
Divide by 255.
Reserved
Table
Section
30) to obtain a 48 MHz clock.
3.5.24) must be toggled from LOW to HIGH for
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
27 of 333
Reset
value
0x00
0x00
Reset
value
0x00
0x00