LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 35

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.41 Start logic signal enable register 1
3.5.42 Start logic reset register 1
Table 45.
This STARTERP1 register enables or disables the start signal bits in the start logic. The bit
assignment is identical to
Table 46.
Writing a one to a bit in the STARTRSRP1CLR register resets the start logic state. The bit
assignment is identical to
clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt
for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared
before being used.
Bit
3:1
4
7:5
31:8 -
Bit
0
3:1
4
7:5
31:8 -
Symbol
APRPIO2_11
to
APRPIO2_9
APRPIO3_0
APRPIO3_3
to
APRPIO3_1
Symbol
ERPIO2_8
ERPIO2_11 to
ERPIO2_9
ERPIO3_0
ERPIO3_3 to
ERPIO3_1
Start logic edge control register 1 (STARTAPRP1, address 0x4004 8210) bit
description
Start logic signal enable register 1 (STARTERP1, address 0x4004 8214) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
-
Value
0
1
0
1
0
1
0
1
-
…continued
Rev. 2 — 7 July 2010
Table
Table
Description
Edge select for start logic input PIO2_11 to PIO2_9
Falling edge
Rising edge
Edge select for start logic input PIO3_0
Falling edge
Rising edge
Edge select for start logic input PIO3_3 to PIO3_1
Falling edge
Rising edge
Reserved
Description
Enable start signal for start logic input PIO2_8
Disabled
Enabled
Enable start signal for start logic input PIO2_11 to
PIO2_9
Disabled
Enabled
Enable start signal for start logic input PIO3_0
Disabled
Enabled
Enable start signal for start logic input PIO3_3 to
PIO1_1
Disabled
Enabled
Reserved
45. The start-up logic uses the input signals to generate a
45.
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
Reset
value
0
0
0
0
0
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