LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 33

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.38 Start logic reset register 0
3.5.39 Start logic status register 0
Table 42.
Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit
assignment is identical to
clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt
for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared
before being used.
Table 43.
This register reflects the status of the enabled start signal bits. The bit assignment is
identical to
or not a wake-up signal has been received for a given pin.
Bit
31:25 ERPIO2_7 to
Bit
0
11:1
12
23:13
24
31:25
Symbol
ERPIO2_1
Symbol
RSRPIO0_0
RSRPIO0_11
to
RSRPIO0_1
RSRPIO1_0
RSRPIO1_11
to
RSRPIO1_1
RSRPIO2_0
RSRPIO2_7
to
RSRPIO2_1
Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit
description
Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit
description
Table
All information provided in this document is subject to legal disclaimers.
41. Each bit (if enabled) reflects the state of the start logic, i.e. whether
Value
0
1
Value
0
1
0
1
0
1
0
1
0
1
0
1
…continued
Rev. 2 — 7 July 2010
Table
Description
Enable start signal for start logic input PIO2_7 to
PIO2_1
Disabled
Enabled
Description
Start signal reset for start logic input PIO0_0
-
Write: reset start signal
Start signal reset for start logic input PIO0_11 to
PIO0_1
-
Write: reset start signal
Start signal reset for start logic input PIO1_0
-
Write: reset start signal
Start signal reset for start logic input PIO1_11 to
PIO1_1
-
Write: reset start signal
Start signal reset for start logic input PIO2_0
-
Write: reset start signal
Start signal reset for start logic input PIO2_7 to
PIO2_1
-
Write: reset start signal
41. The start-up logic uses the input signals to generate a
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
Reset
value
n/a
n/a
n/a
n/a
n/a
n/a
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