LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 64

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
5.6.8 Interrupt Clear-Pending Register 1 register
The ICPR1 register allows clearing the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Setting the pending state of
interrupts is done through the ISPR0 and ISPR1 registers
Section
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 70.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31:25
Name
ICP_PIO2_8
ICP_PIO2_9
ICP_PIO2_10
ICP_PIO2_11
ICP_PIO3_0
ICP_PIO3_1
ICP_PIO3_2
ICP_PIO3_3
ICP_I2C0
ICP_CT16B0
ICP_CT16B1
ICP_CT32B0
ICP_CT32B1
ICP_SSP
ICP_UART
ICP_USBIRQ
ICP_USBFRQ
ICP_ADC
ICP_WDT
ICP_BOD
-
ICP_PIO_3
ICP_PIO_2
ICP_PIO_1
ICP_PIO_0
-
5.6.6).
Interrupt Set-Pending Register 1 register (ISPR1 - address 0xE000 E204) bit
description
All information provided in this document is subject to legal disclaimers.
Description
PIO0_0 start logic input interrupt pending clear.
PIO2_9 start logic input interrupt pending clear.
PIO2_10 start logic input interrupt pending clear.
PIO2_11 start logic input interrupt pending clear.
PIO3_0 start logic input interrupt pending clear.
PIO3_0 start logic input interrupt pending clear.
PIO3_0 start logic input interrupt pending clear.
PIO3_0 start logic input interrupt pending clear.
I
Timer CT16B0 interrupt pending clear.
Timer CT16B1 interrupt pending clear.
Timer CT32B0 interrupt pending clear.
Timer CT32B1 interrupt pending clear.
SSP interrupt pending clear.
UART interrupt pending clear.
USB IRQ interrupt pending clear.
USB FRQ interrupt pending clear.
ADC interrupt pending clear.
WDT interrupt pending clear.
BOD interrupt pending clear.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
GPIO port 3 interrupt pending clear.
GPIO port 2 interrupt pending clear.
GPIO port 1 interrupt pending clear.
GPIO port 0 interrupt pending clear.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
Rev. 2 — 7 July 2010
C0 interrupt pending clear.
Chapter 5: LPC13xx Interrupt controller
(Section 5.6.5
UM10375
© NXP B.V. 2010. All rights reserved.
and
65 of 333