LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 207

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
12.11 Details of I
UM10375
User manual
12.10.10 Status decoder and status register
12.10.8 Timing and control
12.10.9 Control register, I2CONSET and I2CONCLR
via the I
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for I2DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits acknowledge
bits, controls the master and slave modes, contains interrupt request logic, and monitors
the I
The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
will set bits in the I
Conversely, writing to I2CONCLR will clear bits in the I
to ones in the value written.
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
The four operating modes are:
Data transfers in each mode of operation are shown in
Figure
describing the I
•
•
•
•
2
C operating modes
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
2
2
C-bus status.
C control register contains bits used to control the following I
33, and
2
C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
Figure
2
All information provided in this document is subject to legal disclaimers.
C operating modes.
2
2
C control register that correspond to ones in the value written.
C block are used. The 5-bit status code is latched into the five most
2
C control register may be read as I2CONSET. Writing to I2CONSET
34.
Rev. 2 — 7 July 2010
Table 224
2
lists abbreviations used in these figures when
C-bus status. The 5-bit code may be used to
Chapter 12: LPC13xx I2C-bus controller
2
Figure
C control register that correspond
30,
2
Figure
C block functions: start
UM10375
© NXP B.V. 2010. All rights reserved.
31,
Figure
209 of 333
32,