LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 16

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.4 System PLL status register
3.5.5 USB PLL control register
Table 8.
This register is a Read-only register and supplies the PLL lock status (see
Section
Table 9.
The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
the USB block if available (see
This register connects and enables the USB PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock 48 MHz clock used by the USB subsystem.
Remark: The USB PLL must be connected to the system oscillator for correct USB
operation (see
Table 10.
Bit
4:0
6:5
31:7
Bit
0
31:1
Bit
4:0
Symbol
MSEL
PSEL
-
Symbol
LOCK
-
Symbol
MSEL
3.10.1).
System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description
System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Table
All information provided in this document is subject to legal disclaimers.
Value
00000 Division ratio M = 1
...
11111
00
01
10
11
Value
0
1
-
Value
00000 Division ratio M = 1
...
11111
-
18).
Rev. 2 — 7 July 2010
Description
Feedback divider value. The division value M is the
programmed MSEL value + 1.
Division ration M = 32
Post divider ratio P. The division ratio is 2 × P.
P = 1
P = 2
P = 4
P = 8
Reserved. Do not write ones to reserved bits.
Description
PLL lock status
PLL not locked
PLL locked
Reserved
Description
Feedback divider value. The division value M is the
programmed MSEL value + 1.
Division ration M = 32
Section
3.1).
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
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Reset
value
0x000
0x00
0x00
Reset
value
0x0
0x00
Reset
value
0x000