LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 296

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
Table 288. Code Read Protection (CRP) options
Table 289. Code Read Protection hardware/software interaction
Name
NO_ISP
CRP1
CRP2
CRP3
CRP option
None
None
None
CRP1
CRP1
Pattern
programmed in
0x0000 02FC
0x4E69 7370
0x12345678
0x87654321
0x43218765
User Code
Valid
No
Yes
Yes
Yes
Yes
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
Description
Prevents sampling of pin PIO0_1 for entering ISP mode. PIO0_1 is
available for other uses.
Access to chip via the SWD pins is disabled. This mode allows
partial flash update using the following ISP commands and
restrictions:
This mode is useful when CRP is required and flash field updates
are needed but all sectors can not be erased. Since compare
command is disabled in case of partial updates the secondary
loader should implement checksum mechanism to verify the integrity
of the flash.
Access to chip via the SWD pins is disabled. The following ISP
commands are disabled:
When CRP2 is enabled the ISP erase command only allows erasure
of all user sectors.
Access to chip via the SWD pins is disabled. ISP entry by pulling
PIO0_1 LOW is disabled if a valid user code is present in flash
sector 0.
This mode effectively disables ISP override using PIO0_1 pin. It is
up to the user’s application to provide a flash update mechanism
using IAP calls or call reinvoke ISP command to enable flash update
via UART0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
•
•
•
•
•
•
•
•
•
•
PIO0_1 pin at
reset
x
High
Low
High
Low
Write to RAM command cannot access RAM below 0x1000
0300.
Copy RAM to flash command can not write to Sector 0.
Erase command can erase Sector 0 only when all sectors are
selected for erase.
Compare command is disabled.
Read Memory command is disabled.
Read Memory
Write to RAM
Go
Copy RAM to flash
Compare
SWD enabled LPC13xx
Yes
Yes
Yes
No
No
enters ISP
mode
Yes
No
Yes
No
Yes
UM10375
© NXP B.V. 2010. All rights reserved.
partial flash
Update in ISP
mode
Yes
NA
Yes
NA
Yes
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