LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 124
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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9.1 How to read this chapter
9.2 Basic configuration
9.3 Introduction
UM10375
User manual
The USB device controller is available on parts LPC1342 and LPC1343 only.
The USB device is configured using the following registers:
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame
(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 5 logical or 10 physical endpoints. There are four types of
transfers defined for the endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the
rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no
error correction.
For more information on the Universal Serial Bus, see the USB Implementers Forum
website.
The USB device controller on the LPC134x enables full-speed (12 Mb/s) data exchange
with a USB host controller.
Table 150. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation Description
AHB
ATLE
ATX
EOP
EP
1. Pins: The USB pins must be configured in the IOCONFIG register block
2. Power: In the SYSAHBCLKCTRL register, set bit 14
3. Clock: Enable the USB clock by writing to the USBCLKDIV register
UM10375
Chapter 9: LPC13xx USB device controller
Rev. 2 — 7 July 2010
(Section
interface. The USB PHY must be powered through the PDRUNCFG register
(Table
USB clock can be selected from the dedicated USB PLL or the main clock
For details see
52)
6.4.1).
All information provided in this document is subject to legal disclaimers.
Section
Advanced High-performance bus
Auto Transfer Length Extraction
Analog Transceiver
End-Of-Packet
Endpoint
Rev. 2 — 7 July 2010
9.12.2.
(Table
23) for the USB register
© NXP B.V. 2010. All rights reserved.
(Table
User manual
(Table
30). The
126 of 333
28).
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