LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 145
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
9.11.12 Set Endpoint Status (Command: 0x40 - 0x49, Data: write 1 byte
9.11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x47, Data: read 1
Table 176. Select Endpoint command description
byte)
Commands 0x40 to 0x47 are identical to their Select Endpoint equivalents, with the
following differences:
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
Bit Symbol
2
3
4
5
6
7
•
•
•
They clear the bit corresponding to the endpoint in the USBEpIntSt register.
In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
Reading one byte is obligatory.
STP
PO
EPN
B_1_FULL
B_2_FULL
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
-
SETUP bit: the value of this bit is updated after each
successfully received packet (i.e. an ACKed package on that
particular physical endpoint).
The STP bit is cleared by doing a Select Endpoint/Clear
Interrupt on this endpoint.
The last received packet for the selected endpoint was a
SETUP packet.
Packet over-written bit.
The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’
command.
The previously received packet was over-written by a SETUP
packet.
EP NAKed bit indicates sending of a NAK. If the host sends an
OUT packet to a filled OUT buffer, the device returns NAK. If
the host sends an IN token packet to an empty IN buffer, the
device returns NAK.
The EPN bit is reset after the device has sent an ACK after an
OUT packet or when the device has seen an ACK after sending
an IN packet.
The EPN bit is set when a NAK is sent and the interrupt on NAK
feature is enabled.
The buffer 1 status.
Buffer 1 is empty.
Buffer 1 is full.
The buffer 2 status.
Buffer 2 is empty.
Buffer 2 is full.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
147 of 333
Reset
value
0
0
0
0
0
NA
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