D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 1164

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
Rev.4.00 Sep. 07, 2007 Page 1132 of 1210
REJ09B0245-0400
Notes: 1. The method for writing to TCSR is different from that for general registers to prevent
2. Can only be written with 0 for flag clearing.
*1
accidental overwriting. For details, see section 13.2.4, Notes on Register Access.
:
:
:
R/(W)
Overflow Flag
OVF
7
0
0
1
*2
Timer Mode Select
Notes: 1.
[Clearing condition]
When 0 is written to OVF after reading OVF = 1
[Setting condition]
When TCNT overflows from H'FF to H'00 in interval timer mode
0
1
WT/IT
R/W
6
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF
TCNT overflows
2.
Timer Enable
0
1
The WDTOVF pin function is not available in the F-ZTAT versions.
For details of the case where TCNT overflows in watchdog timer
mode, see section 13.2.3, Reset Control/Status Register (RSTCSR).
Note: * The overflow period is the time from when TCNT
TCNT is initialized to H'00 and halted
TCNT counts
TME
R/W
Clock Select
CKS2 CKS1 CKS0
5
0
0
1
starts counting up from H'00 until overflow occurs.
*2
0
1
0
1
—
—
4
1
0
1
0
1
0
1
0
1
H'FFBC (W), H'FFBC (R)
—
—
3
1
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
CKS2
R/W
2
0
CKS1
(when φ = 20 MHz)
R/W
*1
25.6µs
819.2µs
1.6ms
6.6ms
26.2ms
104.9ms
419.4ms
1.68s
Overflow period*
1
0
signal when
CKS0
R/W
0
0
WDT