D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 280

IC H8S/2332 MCU ROMLESS 144QFP

D12332VFC20V

Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12332VFC20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of
transfers, when H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
DTID
DTSZ
MAR = MAR – (–1)
· 2
· ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation,
therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the
CPU or DTC.
By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the
transfer after that terminated when the DTE bit was cleared.
Rev.4.00 Sep. 07, 2007 Page 248 of 1210
REJ09B0245-0400

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