D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 335

IC H8S/2332 MCU ROMLESS 144QFP

D12332VFC20V

Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12332VFC20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.2.7
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8.5, together with the vector numbers
generated by the interrupt controller.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
Bit
Initial value :
R/W
DTC Enable Registers (DTCER)
Description
[Clearing conditions]
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
DTC activation by this interrupt is disabled
DTC activation by this interrupt is enabled
:
:
When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended
DTCE7
R/W
7
0
DTCE6
R/W
6
0
DTCE5
R/W
5
0
DTCE4
R/W
0
4
Rev.4.00 Sep. 07, 2007 Page 303 of 1210
DTCE3
R/W
3
0
DTCE2
R/W
2
0
DTCE1
REJ09B0245-0400
R/W
1
0
(Initial value)
(n = 7 to 0)
DTCE0
R/W
0
0

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