D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 220

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.8
6.8.1
When the chip accesses external space, it can insert a 1-state idle cycle (T
the following two cases: (1) when read accesses in different areas occur consecutively, and (2)
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, etc., with a long output floating time, and
high-speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is
enabled in advanced mode.
Figure 6.31 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev.4.00 Sep. 07, 2007 Page 188 of 1210
REJ09B0245-0400
Address bus
CS (area A)
CS (area B)
RD
Data bus
φ
Idle Cycle
Operation
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Bus cycle A
T
2
Figure 6.31 Example of Idle Cycle Operation (1)
T
3
Long output
floating time
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
RD
Data bus
φ
T
1
Bus cycle A
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
T
2
I
) between bus cycles in
T
3
T
Bus cycle B
I
T
1
T
2