D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 426

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.11.2
Table 9.19 shows the port A register configuration.
Table 9.19 Port A Registers
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open drain control register
Port function control register 1
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
PA
Rev.4.00 Sep. 07, 2007 Page 394 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
0
).
Register Configuration
:
:
:
:
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
PA7DR
R/W
W
7
0
7
0
PA6DR
R/W
W
6
0
6
0
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
PFCR1
PA5DR
R/W
W
5
0
5
0
PA4DR
R/W
W
4
0
4
0
R/W
W
R/W
R
R/W
R/W
R/W
PA3DR
R/W
W
0
0
3
3
Initial Value
H'00
H'00
Undefined
H'00
H'00
H'0F
PA2DR
R/W
W
2
0
2
0
PA1DR
R/W
W
1
0
1
0
H'FF69
H'FF70
H'FF77
Address *
H'FEB9
H'FF59
H'FF45
7
PA0DR
to
R/W
W
0
0
0
0