D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 18

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
7.4
7.5
7.6
7.7
Section 8 Data Transfer Controller
8.1
8.2
Rev.4.00 Sep. 07, 2007 Page xvi of xxx
7.2.4
7.2.5
Register Descriptions (2) (Full Address Mode) ................................................................ 221
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions (3) .................................................................................................. 234
7.4.1
7.4.2
7.4.3
Operation........................................................................................................................... 239
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 267
7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 275
7.5.12 Write Data Buffer Function ................................................................................. 281
7.5.13 DMAC Multi-Channel Operation ........................................................................ 282
7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,
7.5.15 NMI Interrupts and DMAC.................................................................................. 285
7.5.16 Forced Termination of DMAC Operation............................................................ 286
7.5.17 Clearing Full Address Mode ................................................................................ 287
Interrupts ........................................................................................................................... 288
Usage Notes ...................................................................................................................... 289
Overview........................................................................................................................... 295
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 298
DMA Control Register (DMACR)....................................................................... 211
DMA Band Control Register (DMABCR) .......................................................... 215
Memory Address Register (MAR)....................................................................... 221
I/O Address Register (IOAR) .............................................................................. 221
Execute Transfer Count Register (ETCR) ........................................................... 222
DMA Control Register (DMACR)....................................................................... 224
DMA Band Control Register (DMABCR) .......................................................... 228
DMA Write Enable Register (DMAWER) .......................................................... 234
DMA Terminal Control Register (DMATCR)..................................................... 237
Module Stop Control Register (MSTPCR) .......................................................... 238
Transfer Modes .................................................................................................... 239
Sequential Mode .................................................................................................. 241
Idle Mode............................................................................................................. 244
Repeat Mode ........................................................................................................ 247
Single Address Mode........................................................................................... 251
Normal Mode....................................................................................................... 254
Block Transfer Mode ........................................................................................... 257
DMAC Activation Sources .................................................................................. 263
Basic DMAC Bus Cycles..................................................................................... 266
and the DTC......................................................................................................... 284
Features................................................................................................................ 295
Block Diagram..................................................................................................... 296
Register Configuration......................................................................................... 297
................................................................................. 295