D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 397

IC H8S/2332 MCU ROMLESS 144QFP

D12332VFC20V

Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12332VFC20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port 5 Data Register (P5DR)
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5
Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified.
P5DR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior
state in software standby mode.
Port 5 Register (PORT5)
Note: * Determined by state of pins P5
PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 5 pins (P5
Bits 7 to 4 always return the pin states when a port 5 read is performed, without regard to P5DDR.
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5
read is performed while P5DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT5 contents are determined by the pin states, as
P5DDR and P5DR are initialized. PORT5 retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined
P57
R
7
7
P56
R
6
6
3
to P5
7
to P5
P55
0
R
) must always be performed on P5DR.
5
5
0
.
P54
R
4
4
Rev.4.00 Sep. 07, 2007 Page 365 of 1210
P53DR
R/W
P53
— *
R
3
0
3
P52DR
R/W
P52
— *
R
2
0
2
P51DR
REJ09B0245-0400
R/W
P51
— *
R
1
0
1
3
to P5
P50DR
R/W
P50
— *
R
0
0
0
0
).

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