UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 108

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

4.2.7 Port 12
using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register 12 (PU12).
resonator for main system clock connection, external clock input, and resonator for subsystem clock connection.
106
Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
Reset signal generation sets port 12 to input mode.
Figures 4-14 and 4-15 show block diagrams of port 12.
Caution When using P121 to P124 pins to connect a resonator for the main system clock or subsystem
Remark X1 and X2 of the
WR
WR
WR
PU12:
PM12:
RD:
WR
RD
PORT
PM
PU
clock, or to input an external clock, the X1 oscillation mode, XT1 oscillation mode, or external
clock input mode must be set by using the clock operation mode select register (OSCCTL) (for
details, see 5.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation
mode for subsystem clock pin). The reset value of OSCCTL is 00H (all P121 to P124 are I/O port
pins). At this time, settings of PM121 to PM124 and P121 to P124 are not necessary.
(OCD0A, OCD0B) when the on-chip debug function is used. For details, see CHAPTER 27 ON-CHIP
DEBUG FUNCTION ( PD78F0376D AND 78F0386D ONLY).
: Write signal
Pull-up resistor option register 12
Port mode register 12
Read signal
Output latch
Alternate
function
PM120
PU120
(P120)
PM12
PU12
PD78F0376D and 78F0386D can be used as on-chip debug mode setting pins
Figure 4-14. Block Diagram of P120
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17504EJ2V0UD
V
DD
P-ch
P120/INTP0/EXLVI