UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 427

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

LCDSEG
LCDCTL
Cautions 1. Generate a stop condition if an access like the one shown below is made.
Access
(2) Communication format
Note
Remark
target
Read data from each register on the LCD controller/driver starting from the start condition, slave ID, address,
restart condition, slave ID, read data, then stop condition in that order.
continuously performing read/write access from transmissions of the start condition to stop condition. With
this function, the address does not need to be set each time.
With the 78K0/LF2, the address is incremented by one based on the register read/write start address by
2. When SDA0 is fixed at the low level output status due to noise, input 0 to P130 (bit 0 of port
ST:
RST:
SP:
A7 to A0: Addresses for LCDCTL or LCDSEG
RST
RST
RST
<7>
<1>
Figure 16-34. Communication Format for Read Operation (When Reading Twice)
ST
ST
ST
register 13) to reset the LCD controller/driver.
• An access made in a format other than specified
• An access made with a slave ID other than specified
0 1 1 1 0 0 0
0 1 1 1 0 0 1
0 1 1 1 0 0 0
0 1 1 1 0 0 1
Stop condition
Start condition
Restart condition
Slave ID
Slave ID
<2>
<8>
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
R/W
R/W
<3>
<9>
0
0
1
1
D7
D7
Address
LCDCTL : (A7, A6, A5, A4, A3, A2, A1, A0) + 1
LCDSEG: (A7, A6, A5, A4, A3, A2, A1, A0) + 1
<10>
ACK
ACK
ACK
ACK
ACK
ACK
<4>
D6
D6
Note
A7
A7
D7
D7
D5
D5
Address
LCDCTL : A7, A6, A5, A4, A3, A2, A1, A0
LCDSEG: A7, A6, A5, A4, A3, A2, A1, A0
D6
D6
A6
A6
Read data2
D4
D4
<13>
A5
A5
D5
D5
D3
D3
Read dara 1
A4
A4
D4
D4
Address
<11>
<5>
D2
D2
A3
A3
D3
D3
D1
D1
A2
A2
D2
D2
D0
D0
D1
D1
A1
A1
<14>
ACK
NAK
NAK
A0
A0
D0
D0
<12>
ACK
ACK
ACK
ACK
ACK
ACK
<15>
<6>
SP
SP
SP
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