UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 520

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
518
Supply voltage
oscillation clock (f
(when X1 oscillation
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
Remark V
Internal reset signal
Internal high-speed
system clock (f
(V
V
POC
DD
High-speed
is selected)
)
= 1.59 V (TYP.)
2.
1.8 V
2.7 V (TYP.)
CPU
LOW-VOLTAGE DETECTOR).
V
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
RH
XH
Note 1
V
0 V
The operation guaranteed range is 1.8 V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
)
)
LVI
: LVI detection voltage
Operation
: POC detection voltage
stops
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
Set LVI to be
used for reset
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
specified by software.
oscillation clock)
(internal high-speed
Starting oscillation is
Normal operation
and Low-Voltage Detector (2/2)
User’s Manual U17504EJ2V0UD
Note 2
Reset period
(oscillation
stop)
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
used for interrupt
V
Set LVI to be
DD
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
5.5 V. To make the state at lower than 1.8 V reset
Note 2
Reset period
(oscillation
stop)
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 2
Operation stops