UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 372

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

16.5.2 Addresses
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
16.5.3 Transfer direction specification
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
370
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
The slave address and the eighth bit, which specifies the transfer direction as described in 16.5.3 Transfer
The slave address is assigned to the higher 7 bits of IIC0.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
INTIIC0
INTIIC0
SDA0
SCL0
SDA0
SCL0
Figure 16-15. Transfer Direction Specification
A6
A6
1
1
CHAPTER 16 SERIAL INTERFACE IIC0
A5
A5
2
2
User’s Manual U17504EJ2V0UD
Figure 16-14. Address
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
A1
Transfer direction specification
A1
6
6
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note