UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 146

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
144
Status Transition
(B)
(B)
10 MHz)
(B)
(B)
20 MHz)
Status Transition
(B)
(B)
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
already been set.
(C) (X1 clock: 1 MHz
(C) (external main clock: 1 MHz
(C) (X1 clock: 10 MHz < f
(C) (external main clock: 10 MHz < f
(D) (XT1 clock)
(D) (external subsystem clock)
CHAPTER 29 ELECTRICAL SPECIFICATIONS).
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
:
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
f
XH
XH
10 MHz)
20 MHz)
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
f
XH
XH
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17504EJ2V0UD
AMPH
Unnecessary if these registers
XTSTART
0
0
1
1
0
1
0
Note
are already set
Unnecessary if the CPU is operating
EXCLK
0
1
0
1
with the subsystem clock
EXCLKS
0
1
OSCSEL
1
1
1
1
OSCSELS
MSTOP
with the high-speed
Unnecessary if the
CPU is operating
0
0
0
system clock
1
1
0
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
1
1
Note
CSS
MCM0
1
1
1
1
1
1