UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 285

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

13.4 Operation of Serial Interface UART0
13.4.1 Operation stop mode
pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0,
TXE0, and RXE0) of ASIM0 to 0.
(1) Register used
Address: FF70H After reset: 01H R/W
Serial interface UART0 has the following two modes.
In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the
Notes 1.
Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.
Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4
Symbol
ASIM0
The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Operation stop mode
Asynchronous serial interface (UART) mode
2.
To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1.
PORT FUNCTIONS.
POWER0
The input from the R
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
POWER0
RXE0
TXE0
0
<7>
Note 1
0
0
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Disables transmission (synchronously resets the transmission circuit).
Disables reception (synchronously resets the reception circuit).
TXE0
<6>
X
D0 pin is fixed to high level when POWER0 = 0.
CHAPTER 13 SERIAL INTERFACE UART0
RXE0
<5>
User’s Manual U17504EJ2V0UD
Enables/disables operation of internal operation clock
Note 2
.
PS01
4
Enables/disables transmission
Enables/disables reception
PS00
3
CL0
2
SL0
1
0
1
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