UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 362

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

360
(2) IIC status register 0 (IICS0)
Address: FFAAH
Condition for clearing (EXC0 = 0)
Condition for clearing (MSTS0 = 0)
Condition for clearing (ALD0 = 0)
Symbol
MSTS0
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation sets IICS0 to 00H.
Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
Remark
EXC0
When a stop condition is detected
When ALD0 = 1 (arbitration loss)
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
Automatically cleared after IICS0 is read
When IICE0 changes from 1 to 0 (operation stop)
Reset
IICS0
ALD0
0
1
0
1
0
1
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Extension code was not received.
Extension code was received.
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
MSTS0
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
<7>
Bit 7 of IIC control register 0 (IICC0)
After reset: 00H
Figure 16-6. Format of IIC Status Register 0 (IICS0) (1/3)
ALD0
<6>
CHAPTER 16 SERIAL INTERFACE IIC0
EXC0
<5>
Note
2
C.
User’s Manual U17504EJ2V0UD
R
Detection of extension code reception
COI0
<4>
Detection of arbitration loss
Master device status
Condition for setting (EXC0 = 1)
Condition for setting (MSTS0 = 1)
Condition for setting (ALD0 = 1)
When the higher four bits of the received address data is
either “0000” or “1111” (set at the rising edge of the
eighth clock).
When a start condition is generated
When the arbitration result is a “loss”.
TRC0
<3>
ACKD0
<2>
STD0
<1>
SPD0
<0>