UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 360

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

358
Cautions concerning set timing
Condition for clearing (STT0 = 0)
Note This flag’s signal is invalid when IICE0 = 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
STT0
For master reception:
For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during
Cannot be set to 1 at the same time as SPT0.
Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Cleared by loss in arbitration
Cleared after start condition is generated by master device
Cleared by LREL0 = 1 (exit from communications)
When IICE0 = 0 (operation stop)
Reset
Cleared by setting SST0 to 1 while communication
reservation is prohibited.
0
1
Note
Do not generate a start condition.
When bus is released (in STOP mode):
When a third party is communicating:
In the wait state (when master device):
2. IICRSV: Bit 0 of IIC flag register (IICF0)
Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed
Generates a restart condition after releasing the wait.
from high level to low level and then the start condition is generated. Next, after the rated amount of time has
elapsed, SCL0 is changed to low level.
STCF:
When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition
after the bus is released.
When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated.
Bit 7 of IIC flag register (IICF0)
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has
been cleared to 0 and slave has been notified of final reception.
the wait period that follows output of the ninth clock.
Figure 16-5. Format of IIC Control Register 0 (IICC0) (3/4)
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
Start condition trigger
Condition for setting (STT0 = 1)
Set by instruction