UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 500

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Notes1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
Remark f
498
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
8-bit timer/event
counter
8-bit timer
Watch timer
Watchdog timer
Clock output
A/D converter
Serial interface
LCD controller/driver
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
RL
2.
3.
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
f
f
f
f
f
PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, 78F0386D only.
PD78F037x only.
RH
X
EXCLK
XT
EXCLKS
RL
HALT Mode Setting
:
:
:
:
Note3
Note2
:
: External subsystem clock
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
00
01
50
51
H0
H1
UART0
UART6
CSI10
IIC0
Note1
Note1, 2
Note1
Note1
f
f
f
f
f
RH
X
EXCLK
XT
EXCLKS
Note1
Note1
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Operation stopped
Status before HALT mode was set is retained
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable
Operable. However, operation disabled when peripheral hardware clock (f
Operable
Table 21-1. Operating Statuses in HALT Mode (2/2)
When CPU Is Operating on XT1 Clock (f
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
CHAPTER 21 STANDBY FUNCTION
User’s Manual U17504EJ2V0UD
XT
)
Status before HALT mode was set is retained
Operation continues (cannot be stopped)
When CPU Is Operating on External
Subsystem Clock (f
PRS
) is stopped.
EXCLKS
)