UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 134

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

132
Subsystem clock (f
(when XT1 oscillation
oscillation clock (f
(when X1 oscillation
Internal high-speed
Internal reset signal
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
Note
Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MAX.) from power application until the
<2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MAX.), the CPU starts operation on the
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling high-
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
system clock (f
Power supply
voltage (V
High-speed
CPU clock
oscillator automatically starts oscillation.
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (3) in 5.6.3
Example of controlling subsystem clock).
selected)
selected)
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal
high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1
oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation
stabilization time select register (OSTS).
DD
SUB
0 V
RH
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
XH
Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On
)
)
)
)
<1>
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the
voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE
= 1) (see Figure 5-13). By doing so, the CPU operates with the same timing as <2> and
thereafter in Figure 5-12 after reset release by the RESET pin.
from the EXCLK and EXCLKS pins is used.
1.59 V
(TYP.)
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
<3> Waiting for
voltage stabilization
<2>
Waiting for oscillation
accuracy stabilization
0.5 V/ms
(3.24 ms (TYP.))
(MAX.)
1.8 V
Starting X1 oscillation
is specified by software.
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17504EJ2V0UD
Starting XT1 oscillation
is specified by software.
Internal high-speed oscillation clock
Reset processing
<4>
(20 s (TYP.))
oscillation stabilization time:
<4>
2
11
/f
X1 clock
X
to 2
16
/f
X
Note
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock