UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 113

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(4) A/D port configuration register (ADPC) ( PD78F037x only)
Cautions 1. Set the channel used for A/D conversion in the input mode by using port mode register 2
This register switches the P20/ANI0 to P27/ANI7 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Symbol
Address: FF2FH
ADPC
2. Do not set a pin to be used as a digital I/O pin with ADPC with ADS.
3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
(PM2).
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
ADPC3
7
0
0
0
0
0
0
0
0
0
1
Figure 4-19. Format of A/D Port Configuration Register (ADPC)
After reset: 00H
ADPC2
Other than above
0
0
0
0
1
1
1
1
0
6
0
ADPC1
CHAPTER 4 PORT FUNCTIONS
0
0
1
1
0
0
1
1
0
5
0
User’s Manual U17504EJ2V0UD
R/W
ADPC0
0
1
0
1
0
1
0
1
0
4
0
ANI7
P27/
Setting prohibited
D
A
A
A
A
A
A
A
A
ADPC3
Analog input (A)/digital input (D) switching
3
ANI6
P26/
A
A
A
A
A
A
A
D
D
ANI5
P25/
A
A
A
A
A
A
D
D
D
ADPC2
2
ANI4
P24/
A
A
A
A
A
D
D
D
D
ANI3
P23/
A
A
A
A
D
D
D
D
D
ADPC1
1
ANI2
P22/
A
A
A
D
D
D
D
D
D
ANI1
P21/
A
A
D
D
D
D
D
D
D
ADPC0
0
ANI0
P20/
D
D
D
D
D
D
D
D
A
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