UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 363

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Condition for clearing (TRC0 = 0)
<Both master and slave>
<Master>
<Slave>
<When not used for communication>
Condition for clearing (COI0 = 0)
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Cleared by WREL0 = 1
When ALD0 changes from 0 to 1 (arbitration loss)
Reset
When “1” is output to the first byte’s LSB (transfer
direction specification bit)
When a start condition is detected
When “0” is input to the first byte’s LSB (transfer direction
specification bit)
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
TRC0
Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
Remark
COI0
0
1
0
1
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
Note
Figure 16-6. Format of IIC Status Register 0 (IICS0) (2/3)
(wait cancel)
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
Condition for setting (TRC0 = 1)
<Master>
<Slave>
When the received address matches the local address
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
When a start condition is generated
When “0” is output to the first byte’s LSB (transfer
direction specification bit)
When “1” is input to the first byte’s LSB (transfer
direction specification bit)
361