UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 437

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Symbol
Address: LCDCTL's 02H
LCDC
(3) LCD clock control register (LCDC)
LCDC3
LCDC1
LCDC specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC to 00H.
Note Specify an LCD source clock (f
Cautions 1. Bits 4 to 7 must be set to 0.
Cautions 1. Bits 3 and 4 must be set to 0.
0
1
1
0
0
1
1
7
0
A. To stop voltage boosting after switching display status from on to off:
LCDC2
LCDC0
2. Before changing the LCDC setting, be sure to stop voltage boosting (VLCON = 0).
3. Set the frame frequency to 128 Hz or lower.
2. When operating VLCON, follow the procedure described below.
×
0
1
0
1
0
1
B. To stop voltage boosting during display on status:
C. To set display on from voltage boosting stop status:
After reset:
Setting prohibited. Be sure to stop voltage boosting after setting display off.
1) Start voltage boosting by setting VLCON = 1, then wait for voltage boost wait time
2) Set all the segment buffers and common buffers to non-display output status
3) Set display on by setting LCDON = 1.
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting
3) Stop voltage boosting by setting VLCON = 0.
6
0
f
f
f
f
f
f
f
PCL
PCL
PCL
LCD
LCD
LCD
LCD
(t
by setting SCOC = 1.
SCOC = 0.
/2
/2
/2
/2
/2
/2
VAWAIT
(Clock generated by clock output controller)
Figure 17-7. Format of LCD Clock Control Register
2
6
7
8
9
) (see CHAPTER 29 ELECTRICAL SPECIFICATIONS).
00H
CHAPTER 17 LCD CONTROLLER/DRIVER
5
0
R/W
LCD
User’s Manual U17504EJ2V0UD
) frequency of at least 32 kHz.
4
0
LCD source clock (f
LCD clock (LCDCL) selection
LCDC3
3
LCD
) selection
LCDC2
2
Note
LCDC1
1
LCDC0
0
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