UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 149

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5.6.7 Condition before changing CPU clock and processing after changing CPU clock
Internal high-
speed oscillation
clock
X1 clock
External main
system clock
Internal high-
speed oscillation
clock
X1 clock
External main
system clock
Internal high-
speed oscillation
clock
X1 clock
External main
system clock
XT1 clock,
external
subsystem clock
Before Change
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
CPU Clock
X1 clock
External main
system clock
Internal high-
speed oscillation
clock
XT1 clock
External
subsystem clock
Internal high-
speed oscillation
clock
X1 clock
External main
system clock
After Change
Stabilization of X1 oscillation
Enabling input of external clock from EXCLK
pin
Oscillation of internal high-speed oscillator
Stabilization of XT1 oscillation
Enabling input of external clock from
EXCLKS pin
Oscillation of internal high-speed oscillator
and selection of internal high-speed
oscillation clock as main system clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
Enabling input of external clock from EXCLK
pin and selection of high-speed system
clock as main system clock
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization time
MSTOP = 0, OSCSEL = 1, EXCLK = 1
RSTOP = 0
XTSTART = 0, EXCLKS = 0,
After elapse of oscillation stabilization time
XTSTART = 0, EXCLKS = 1,
OSCSELS = 1
RSTOP = 0, MCS = 0
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization time
MCS = 1
MSTOP = 0, OSCSEL = 1, EXCLK = 1
MCS = 1
OSCSELS = 1, or XTSTART = 1
CHAPTER 5 CLOCK GENERATOR
Table 5-6. Changing CPU Clock
Condition Before Change
User’s Manual U17504EJ2V0UD
X1 oscillation can be stopped (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
Internal high-speed oscillator can be
stopped (RSTOP = 1).
Clock supply to CPU is stopped for 5 s
(MIN.) after AMPH has been set to 1.
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
Clock supply to CPU is stopped for 5 s
(MIN.) after AMPH has been set to 1.
Processing After Change
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