UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 393
UPD78F0386GK-8EU-A
Manufacturer Part Number
UPD78F0386GK-8EU-A
Description
MCU 96KB FLASH 5KB RAM
Manufacturer
Renesas Electronics America
Series
78K0/Lx2r
Datasheet
1.UPD78F0372GK-8EU-A.pdf
(624 pages)
Specifications of UPD78F0386GK-8EU-A
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- Current page: 393 of 624
- Download datasheet (5Mb)
An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I
Remark
Interrupt servicing completed
INTIIC0 generated
does not match.
processing returns from the interrupt (the ready flag is cleared).
remaining in the wait state.
Set ready flag
SPD0 = 1?
STD0 = 1?
<1> to <3> above correspond to <1> to <3> in Figure 16-26 Slave Operation Flowchart (2).
No
No
<3>
If the address matches, the communication mode is set, wait is cancelled, and
Figure 16-26. Slave Operation Flowchart (2)
Yes
Yes
CHAPTER 16 SERIAL INTERFACE IIC0
<1>
<2>
User’s Manual U17504EJ2V0UD
Set communication mode flag
Communication direction flag
Clear ready flag
COI0 = 1?
TRC0
Yes
No
Clear communication direction
communication mode flag
flag, ready flag, and
2
C bus
391
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