UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 365

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Symbol
IICF0
Address: FFABH
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
Remark
Condition for clearing (IICRSV = 0)
Condition for clearing (STCEN = 0)
Condition for clearing (STCF = 0)
Condition for clearing (IICBSY = 0)
IICBSY
IICRSV
STCEN
STCF
STCF
Cleared by instruction
Reset
Detection of stop condition
Reset
<7>
Cleared by STT0 = 1
When IICE0 = 0 (operation stop)
Reset
Detection of stop condition
When IICE0 = 0 (operation stop)
Reset
0
1
0
1
0
1
0
1
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
Bus release status (communication initial status when STCEN0 = 1)
Bus communication status (communication initial status when STCEN0 = 0)
Enable communication reservation
Disable communication reservation
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
STT0: Bit 1 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
IICBSY
After reset: 00H
<6>
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Figure 16-7. Format of IIC Flag Register 0 (IICF0)
5
0
CHAPTER 16 SERIAL INTERFACE IIC0
R/W
User’s Manual U17504EJ2V0UD
Communication reservation function disable bit
4
0
Note
3
0
Initial start enable trigger
I
2
STT0 clear flag
C bus status flag
Condition for setting (IICRSV = 1)
Condition for setting (STCF = 1)
Condition for setting (IICBSY = 1)
Condition for setting (STCEN = 1)
2
0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
Set by instruction
Generating start condition unsuccessful and STT0
Detection of start condition
Setting of IICE0 when STCEN = 0
Set by instruction
STCEN
<1>
IICRSV
<0>
363