MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 100

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Generator Module (CGM)
PLLON — PLL On Bit
BCS — Base Clock Select Bit
PCTL3–PCTL0 — Unimplemented
8.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
AUTO — Automatic Bandwidth Control Bit
100
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See
Circuit. Reset sets this bit so that the loop can stabilize as the MCU is powering up.
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. See
Selector
These bits provide no function and always read as logic 1s.
•
•
•
•
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = PLL on
0 = PLL off
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
1 = Automatic bandwidth control
0 = Manual bandwidth control
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Circuit. Reset and the STOP instruction clear the BCS bit.
Address:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. See
8.3.3 Base Clock Selector
Reset:
Read:
Write:
$001D
AUTO
Bit 7
Figure 8-5. PLL Bandwidth Control Register (PBWC)
0
= Unimplemented
LOCK
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
ACQ
Circuit.
5
0
NOTE
XLD
4
0
3
0
0
2
0
0
8.3.3 Base Clock Selector
1
0
0
8.3.3 Base Clock
Freescale Semiconductor
Bit 0
0
0