M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 142

IC M16C/TINY MCU FLASH 48LQFP

M30262F8GP#U7

Manufacturer Part Number
M30262F8GP#U7
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets

Specifications of M30262F8GP#U7

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Clock Asynchronous Serial I/O (UART) Mode
134
Figure 1.15.20. Typical transmit timing in UART mode (UART2)
Figure 1.15.21. Typical receive timing in UART mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
RxDi
Transfer clock
Receive
complete flag
Receive interrupt
request bit
BRGi count
source
Receive enable bit
RTSi
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
2
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
1
0
1
0
1
0
1
0
1
0
1
0
L
1
0
H
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Reception triggered when transfer clock
is generated by falling edge of start bit
The above timing applies to the following settings :
* Parity is disabled.
* One stop bit.
* RTS function is selected.
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 1 .
Start
ST
bit
D
Data is set in UART2 transmit buffer register
0
D
Start bit
1
Tc
D
2
D
Sampled L
3
Renesas Technology Corp.
D
4
D
5
D
6
Cleared to 0 when interrupt request is accepted, or cleared by software
D
Parity
7
bit
P
D
SP
0
Stop
bit
Transferred from UART2 transmit buffer register to UARTi transmit register
Receive data taken in
Transferred from UARTi receive register to
UARTi receive buffer register
Cleared to 0 when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
ST
Note
D
0
D
D
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
2
D
D
3
7
D
4
D
5
D
6
Stop bit
D
7
P
1SIO
SP
M16C/26 Group
, f
2SIO
, f
8SIO
, f
32SIO
)

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