M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 60

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupts
52
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When changing an interrupt control register at a point where the interrupt is disabled, please read the
following precautions on instructions used before changing the register.
(1) Changing a non-interrupt request bit (interrupt priority level)
(2) Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, it is possible that the interrupt request bit is overwritten (reset to "0") and
consequently the interrupt is ignored. This will depend on the instruction used. If this creates problems,
use the instructions below to change the register.
Instructions : AND, OR, BCLR, BSET
is not cleared sometimes. This will depend on the instruction used. If this creates problems, use the
instructions below to change the register.
Instructions : MOV
Example 1:
Example 2:
Example 3:
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
FLG
; Disable interrupts.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
; Disable interrupts.
; Dummy read.
; Enable interrupts.
; Push Flag register onto stack
; Disable interrupts.
; Enable interrupts.
Renesas Technology Corp.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/26 Group