M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 208

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

200
CPU Rewrite Mode (Flash Memory Version)
Status Register
The status register shows the operating state of the flash memory and whether erase operations and
programs ended successfully or in error. It can be read only in the EW0 mode, in the following ways. The
status cannot be read out in the EW1 mode and during suspend.
Table 1.20.2 shows the status register.
In the EW1 mode, the status corresponding to the below is stored in the flash memory control register 0.
Read this register for status check.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (50
After a reset, the status register is set to “80
Each bit in this register is explained below.
Sequencer status (SR7) / FMR00
Erase status (SR5) / FMR07
Program status (SR4)
(1) By reading an arbitrary even address from the user ROM area after writing the read status register
(2) By reading an arbitrary even address from the user ROM area in the period from when the program
After power-on, the sequencer status is set to 1(ready).
The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy)
during write or erase operation and is set to “1” upon completion of these operations.
The erase status informs the operating status of erase operation to the CPU. When an erase error
occurs, it is set to “1”.
The erase status is reset to “0” when cleared.
The program status informs the operating status of write operation to the CPU. When a write error
occurs, it is set to “1”.
The program status is reset to “0” when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (20
(SR5) are set to “1”.
When the program status or erase status =“1”, only the following flash commands will be accepted:
Read Array, Read Status Register, and Clear Status Register.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
command (70
starts or erase operation starts to when the read array command (FF
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (77
(20
entered, read array is assumed and the command that has been set up in the first bus cycle is
canceled.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
16
/D0
16
16
16
), or erase all unlock blocks (A7
) is not the confirmation command (D0
)
Renesas Technology Corp.
16
”.
16
16
/D0
)
16
16
) is not the D0
), both the program status and erase status
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
16
or FF
) is input
16
16
. However, if FF
/D0
M16C/26 Group
16
), block erase
16
is