M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 46

IC M16C/TINY MCU FLASH 48LQFP

M30262F8GP#U7

Manufacturer Part Number
M30262F8GP#U7
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets

Specifications of M30262F8GP#U7

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Oscillation Stop Detection
38
Stop Mode
Wait Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 0007
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
remains above 2V.
Because the oscillation , BCLK, f
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Port pins retain their status from before stop mode is entered.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop
mode, that interrupt must first have been enabled, and the priority level of the interrupts which are not used
to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only
a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupts
to 0, then shift to stop mode.
The main clock division select bit 0 (bit 6 at address 0006
medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from
high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is
retained.
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock f
does not stop so that the peripherals using f
puter is running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”.
Port pins retain their status from before wait mode is entered.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupts which are not used to cancel
must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed
is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hard-
ware reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupts to 0,
then shift to wait mode.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
1
to f
32
Renesas Technology Corp.
, f
1SIO2
C32
do not contribute to the power saving. When the microcom-
to f
32SIO2
16
, f
C
) changes to “1” when shifting from high-speed/
, f
C32
16
, and f
) stops all oscillation and the microcom-
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
AD
stops in stop mode, peripheral
M16C/26 Group
C32
CC

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