M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 155

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UART2 Special Mode Register 3
UART2 Special Mode Register 3
Table 1.15.16. Functions changed by clock phase set bits
Figure 1.15.30. Functions changed by clock phase set bits
Function
SCL initial and last value
Transfer interrupt factor
Data transfer times from UART
receive shift register to receive
buffer register
Bit 1 of UART2 special mode register 3 (address 0375
shows UART2 special mode register 3.
When both the IIC mode select bit (bit 0 of UART2 special mode select register) and the IIC mode select
bit 2 (bit 0 of U2SMR2 register) are “1”, functions changed by these bits are shown in table 1.15.16 and
figure 1.15.30.
Bits 5 to 7 of UART2 special mode register 3 are SDA digital delay setting bits. By setting these bits, it is
possible to turn the SDA delay OFF or set the BRG count source delay to 2 to 8 cycles.
(1) CKPH= "0" (IICM=1, IICM2=1)
SCL
SDA
SCL
SDA
(2) CKPH= "1" (IICM=1, IICM2=1)
(Internal clock, transfer data 9 bits long and MSB first selected.)
(Internal clock, transfer data 9 bits long and MSB first selected.)
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
D7
D7
D
D
6
6
D
D
5
5
CKPH = 0, IICM = 1, IICM2 = 1
Initial value = H, last value = L
Rising edge of 9th bit
Falling edge of 9th bit
Renesas Technology Corp.
D
D
4
4
D
D
3
3
D
D
16
2
2
) are used to clock phase set bit. Figure1.15.9
Transfer to receive buffer
Receive interrupt
Receive interrupt
D
D
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transfer to receive buffer
CKPH = 1, IICM = 1, IICM2 = 1
Initial value = L, last value = L
Falling edge of 10th bit
Two times :falling edge of 9th bit
and rising edge of 9th bit
D
D
0
0
D
D
Transmit interrupt
8
8
Transmit interrupt
M16C/26 Group
147