M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 61

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupts
Interrupt Sequence
Figure 1.9.4. Interrupt response time
Interrupt request generated
This section describes an interrupt sequence — what are performed over a period from the time an inter-
rupt is accepted until the time the interrupt routine is executed .
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor operates in the following sequence:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
00000
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63,
is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
'Interrupt response time' is the period between the time an interrupt occurs and the time the first instruc-
tion within the interrupt routine has been executed. This time comprises the period from the occurrence
of an interrupt to the completion of the instruction under execution at that moment (a) and the time
required for executing the interrupt sequence (b). Figure 1.9.4 shows the interrupt response time.
16
. After this, the corresponding interrupt request bit becomes “0”.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Instruction
(a)
Interrupt response time
Interrupt request acknowledged
Renesas Technology Corp.
Interrupt sequence
(b)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
interrupt routine
Instruction in
M16C/26 Group
Time
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