M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 62

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupts
54
Table 1.9.5. Time required for executing the interrupt sequence
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.9.5. Time required for executing the interrupt sequence
Table 1.9.6. Relationship between interrupts without interrupt priority levels and IPL
BCLK
Address bus
R
W
Interrupt vector address
Data bus
Variation of IPL when Interrupt Request is Accepted
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
V
Software, address match, DBC, single-step
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.9.5.
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 1.9.6 is set in the IPL. Shown in Table 1.9.6 are the IPL values of software and special interrupts
when they are accepted.
DET4
Odd (Note 2)
Odd (Note 2)
interrupt or of a single-step interrupt.
detection
Even
Even
Interrupt sources without priority levels
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
1
Address
0000
information
2
Interrupt
Stack pointer (SP) value
3
4
Even
Even
Odd
Odd
Indeterminate
Indeterminate
5
Renesas Technology Corp.
Indeterminate
6
7
8
6-Bit bus, without wait
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
SP-2
9
contents
SP-2
10
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SP-4
11
contents
SP-4
Level that is set to IPL
12
Not changed
13
vec
contents
vec
8-Bit bus, without wait
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
14
7
M16C/26 Group
vec+2
15
contents
vec+2
16
17
PC
18