M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 83

IC M16C/TINY MCU FLASH 48LQFP

M30262F8GP#U7

Manufacturer Part Number
M30262F8GP#U7
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets

Specifications of M30262F8GP#U7

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30262F8GP#U7M30262F8GP
Manufacturer:
NA
Quantity:
20 000
Company:
Part Number:
M30262F8GP#U7M30262F8GP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30262F8GP#U7M30262F8GP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30262F8GP#U7M30262F8GP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30262F8GP#U7M30262F8GP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
DMAC
Figure 1.11.6. An example of DMA transfer effected by external factors
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to “1”. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.11.6 shows the DMA transfer effected by external factors.
INT0
DMA0
request bit
INT1
BCLK
DMA0
DMA1
CPU
DMA1
request bit
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
Renesas Technology Corp.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/26 Group
Obtainment
of the bus
right
75

Related parts for M30262F8GP#U7